1. Technical Field
The present invention relates generally to electrical and electronic circuits and systems fabricated on printed wiring boards and more specifically to a computer program product embodying a method for balancing power plane pin currents and printed wiring board having balanced pin currents.
2. Description of the Related Art
Printed wiring boards (PWBs), also referred to as printed circuit boards (PCBs) have been in use for decades for fabricating circuits and entire systems. The PWBs provide the interconnects for discrete and integrated components and subsystems and provide power paths or power planes for interconnecting the components to power supplies.
Power distribution in PWBs has always been a concern and in particular, high current systems such as today's processing systems and interchangeable processing sub-units (“blades”) require the handling of very high currents per PWB on some power supply connections, which can generate substantial voltage drops within the PWB conductor(s) and require multiple connector pins or other connector contacts connected in parallel to carry the amount of current supplied to a particular power supply distribution net.
To alleviate the voltage drop problem (and also provide electromagnetic shielding), processing systems and subsystems integrated on a PWB typically use specific layers of a multilayer PWB to carry the power supply voltages and returns or may include a few other connections, but will primarily be power supply layers. A layer dedicated to power supply distribution may actually include multiple power planes distributing two or more separate power supply outputs or may be dedicated to distributing a single power supply output.
The large metal areas typically used for power planes reduces the voltage drop to the connector pins or other terminals used to connect the PWB to a power supply. However, differential voltages exist between the power supply terminal connections, even with a continuous metal plane, because of differing resistive path lengths between the terminals and the current sinks or sources (e.g., a large current consumer such as a processor) and the individual terminals. Additionally, the current distribution in the power plane metal, which is not uniform, contributes to the differential voltages between the terminals, and the differential voltages cause non-uniform distribution of terminal currents. In general: 1) terminals that are closer to the current sources and sinks (i.e., the device power terminals) on the PWB carry more current due to the shorter paths; and 2) terminals that are toward the outside of the terminal array carry higher currents due to the decreased current density away from the center of the connector length (because of lowered voltage drop per unit length along the paths passing through lower current density regions). Both of the above-recited factors superimpose to yield a particular terminal current distribution for each power plane and for each PWB/terminal configuration.
In present-day systems, such as large scalable server systems operating at relatively low voltages, the current levels per PWB and per-terminal are very large. As such, a significant amount of power is dissipated in the connectors due to pin resistance and in the PWBs themselves due to the finite conductivity of the metal layers used to implement the power planes. The use of thin laminated PWBs having many layers also increases the effective resistance of the paths between devices on the PWB and the connector terminals, leading to an increase in the terminal current distribution described above.
The disparity in terminal currents leads to a need to over-specify a connector for pin current handling, which is typically set by the maximum power dissipation through the pin and the overall tolerable pin resistance (dictated by the maximum voltage drop(s) to the components on the PWB). Alternatively, an increase in the total number of terminals required to couple the power supply to the PWB power plane(s) is required.
Also, overall power dissipation is increased by a disparate terminal current distribution. Because the power dissipation per terminal (both in the power plane and the connector pin) is a function of the square of the current through the terminal, the average power dissipation in a connector is not constant over all the possible terminal current distributions, but is at a minimum when the terminal current distribution is equal. For example, for two terminals carrying a total of 4 A, if the pin currents are equal, the power dissipation in watts is 8R where R is the resistance of the pins. If the pin currents are 1 A and 3 A respectively, the power dissipation in watts is 10R. Equalizing the terminal current distribution minimizes the power dissipation in the connector, as well as generally minimizing average power dissipation in the power plane metal area.
It is therefore desirable to provide a method for PWB power plane design and a PWB power plane implementation that equalizes the connector terminal currents for power supply connections.